1. Field of the Invention
The present invention relates to a solid-state image pickup device having a transfer register with an overflow drain.
2. Description of the Related Art
According to a conventional technique, when overflow control is carried out in a transfer register of a CCD solid-state image pickup device, an overflow barrier is formed at the side of a polycrystal silicon layer serving as a lower layer constituting a storage electrode of the transfer register by a polycrystal silicon layer serving as an upper layer and an implant for a barrier.
FIG. 5 is a schematic diagram (plan view) showing a conventional overflow controlling structure.
As shown in FIG. 5, first-layer transfer electrodes 51 and second-layer transfer electrodes 52 are alternately arranged on a transfer register 50. The first-layer transfer electrodes 51 serve as storage electrodes St1, St2, and the second-layer transfer electrodes 52 serve as transfer electrodes Tr1, Tr2.
A first-phase driving pulse xcfx861 is applied as driving pulses xcfx86St1, xcfx86Tr1 to the storage electrode St1 and the transfer electrode Tr1 respectively, and a second-phase driving pulse xcfx862 is applied as driving pulses xcfx86St2, xcfx86Tr2 to the storage electrode St2 and the transfer electrode Tr2, respectively. Further, an overflow control gate OFCG and an overflow drain OFD are provided at the side of the first-phase storage electrode St1 disposed substantially at the center of FIG. 5.
FIG. 6 is a cross-sectional view taken along Y-Yxe2x80x2 of FIG. 5.
As shown in FIGS. 5 and 6, the overflow control gate OFCG comprises a gate electrode 54 and an Nxe2x88x92 area 56. The gate electrode 54 is formed of the same second-layer polycrystal silicon layer as the second-layer transfer electrodes 52 constructing the transfer electrodes Tr1, Tr2. A driving pulse xcfx86OFCG is applied to the gate electrode 54.
In the Nxe2x88x92 area 56, N-type impurities are ion-implanted into a P-type well region 2 of a semiconductor substrate 1.
The overflow drain OFD is constructed by an N++ area 55 which is formed by ion-implanting high-concentration N-type impurities into the P-type well region 2 of the semiconductor substrate 1. In FIG. 5, reference numeral 3 represents an N+ area formed below the storage electrodes St1, St2, and charges under transfer are accumulated in the area 3.
FIG. 7 is a potential diagram along Y-Yxe2x80x2 of FIG. 5.
As shown in FIG. 7, the overflow control gate OFCG based on the gate electrode 54 and the Nxe2x88x92 area 56 serves as a barrier, and charges flowing over the barrier are discarded to the overflow drain OFD.
With this construction, factors affecting the height of the barrier of the overflow control gate OFCG are the length of a portion of the gate electrode 54 of the overflow control gate OFCG that is not overlapped with the first-phase storage electrode St1, that is, the effective length of the overflow control gate OFCG, and the concentration of the impurities in the Nxe2x88x92 area 56, etc.
FIG. 8 is a timing chart showing the driving pulses in the construction of FIG. 5.
The driving pulse xcfx86St1 of the first-phase storage electrode ST1 and the driving pulse xcfx86Tr1 of the first-phase transfer electrode Tr1 are commonly applied by the same driving pulse (first-phase driving pulse xcfx861), and the driving pulse xcfx86St2 of the second-phase storage electrode ST2 and the driving pulse xcfx86 Tr2 of the second-phase transfer electrode Tr2 are commonly applied by the same driving pulse (second-phase driving pulse xcfx862). The first-phase driving pulse and the second-phase driving pulse xcfx862 are opposite to each other in phase. The driving pulse xcfx86 OFCG of the overflow control gate OFCG has the same phase as the first-phase driving pulse xcfx861.
With this setting, the following charge transfer and overflow operation is carried out.
When the first-phase driving pulse xcfx861 is in high level Hi and charges exist in the first-phase storage electrode St1, the driving pulse xcfx86 OFCG of the overflow control gate OFCG is also in high level Hi and thus the overflow barrier is low in height, so that overflow can be induced with a predetermined amount of charges.
On the other hand, when the first-phase driving pulse xcfx861 is in low level Lo and charges are transferred from the first-phase storage electrode St1 to the adjacent second-phase electrodes Tr2, St2, the driving pulse xcfx86 OFCG of the overflow control gate OFCG is also in low level Lo and thus the overflow barrier is high in height, so that the charges under transfer can be prevented from flowing over the barrier.
However, in the case of the above conventional technique, if a positional displacement occurs between the first-phase storage electrode St1 formed of the first-layer polycrystal silicon layer serving as the lower layer and the gate electrode 54 of the overflow control gate OFCG formed of the second-layer polycrystal silicon layer serving as the upper layer, the effective length L1 of the overflow control gate OFCG would vary.
If the effective length L1 varies, the height of the barrier based on the overflow control gate OFCG is also varied. Further, the relationship between the effective length L1 and the effective length L of the transfer electrode Tr1 which determines the height of the barrier of the transfer channel 50 is also varied.
In addition, the height of the barrier based on the overflow control gate OFCG is also varied due to the positional displacement between the Nxe2x88x92 area 56 and the gate electrode 54, the dispersion in line width among the polycrystal silicon layer 51 serving as the lower layer and the polycrystal silicon layers 52, 54 serving as the upper layer, etc.
When the dispersion such as the positional displacement or the like is large, the difference between the barrier height of the overflow control gate OFCG and the barrier height of the transfer electrode Tr1 decreases or excessively increases, so that there occurs such a case that the overflow control cannot be properly performed. This problem obstructs the fine control and microstructuring design of solid-state image pickup devices.
Therefore, an object of the present invention is to provide a solid-state image pickup device for performing proper overflow control.
In order to attain the above object, there is provided a solid-state image pickup device in which a transfer register is provided with an overflow control gate and an overflow drain, and the gate electrode of the overflow control gate is formed so as to be superposed on the lower-layer electrodes of the transfer register side and the overflow drain side.
According to the solid-state image pickup device of the present invention, since the gate electrode of the overflow control gate is formed so as to be superposed on the lower-layer electrodes of the transfer register side and the overflow drain side, the effective length of the overflow control gate is determined by the interval between the lower-layer electrodes of the transfer register side and the overflow drain side.